This invention is directed to the fabrication of n-channel and p-channel (Al,Ga)As Heterostructure Insulated Gate Field-Effect Transistors (HIGFETs) on a common planar wafer surface to form high performance GaAs based complementary integrated circuits. The heterostructure used for HIGFETs consists of an undoped GaAs buffer layer grown on a semi-insulating GaAs substrate followed by an undoped (Al,Ga)As gate layer. Both of these layers are epitaxially grown under conditions to make them as close to intrinsic and insulating as possible. Both the n- and p-channel HIGFETs utilize the high mobility, two-dimensional (2D) electron (hole) gas which is induced at the (Al,Ga)As-GaAs hetero-interface by the application of a suitable gate bias voltage. A self-aligned gate (SAG) process is used to form the source drain regions of the transistors with p.sup.+ implanted regions for p-channel and n.sup.+ implanted regions for n-channel HIGFETs. The electrons (holes) in the channel come from the source drain contacts when a suitable gate bias is applied. The use of undoped heterostructures allows both n- and p-channel transistors to be fabricated in the same epitaxial layers on the same wafer surface by a planar process. The absence of impurities also leads to high electron (hole) channel mobility resulting in FE operation in the saturation velocity regime for high transconductance transistors. Complementary GaAs based circuits which utilize both n- and p-channel transistors offer significant advantages over circuits utilizing only n-channel transistors in terms of noise margin and power dissipation and consequently circuit integration level.
The prior art has not taught this type of complementary planar structure in which both the n- and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel. An article by Katayama et al, "A New Two-Dimensional Electron Gas Field-Effect Transistor Fabricated on Undoped AlGaAs-GaAs Heterostructure", Jpn. J. Appl. Phys., Vol. 23, L150-2, March 84, shows an n-channel device which utilizes an undoped AlGaAs gate and is a 2D electron gas field-effect transistor. It is not a complementary device. Solomon et al, "A GaAs Gate Heterojunction FET", IEEE Electron Device Letters, Vol. 5, No. 9, September 84, p 379-80, describe an n-channel heterostructure FET with an insulating gate but this also is not a complementary device. A different kind of complementary device is shown in an article by Kiehl et al, "Complementary p-MODFET and n-HB MESFET (Al,Ga)As Transistors", IEEE Electron Device Letters, Vol. EDL-5, No. 12, December '84, p 521-23. A similar disclosure is shown in Kiehl et al, "Complementary p-MODFET and n-HB MESFET (Al,Ga)As FET's", IEDM '84, p 854-55. Both of these publications describe a complementary device structure consisting of a conventional p-channel MODFET, made with a doped (Al,Ga)As gate and an n-channel MESFET. This is not a planar device and does not utilize a 2-dimensional electron and hole gas in an undoped high mobility channel for both the n- and p-channel devices. In the substantially different JFET technology, the fabrication of n-channel and p-channel GaAs-based devices on the same wafer has been disclosed, as for example by Zuleeg et al, "Double-Implanted GaAs Complementary JFET's", IEEE Electron Device Letters, Vol. EDL-5, No. 1, January 1984, p 21-23. J-FET devices do not utilize 2-dimensional electron (hole) gases in undoped, high mobility channels.
This subject matter herein is related to a copending application of Cirillo et al, Ser. No. 668,586 filed Nov. 5, 1984, titled "Self-aligned Gate Process for ICs based on Modulation Doped (Al,Ga)As/GaAs FETs", now U.S. Pat. No. 4,662,058 and assigned to the same assignee as the present invention. The self-aligned gate process of that application is also used in the present invention.
The HIGFET approach takes maximum advantage of the heterostructure technology to create two-dimensional (2D) gases of both electrons and holes in a planar undoped multilayer (Al,Ga)As/GaAs structure. The 2D, electron (hole) gas is created at the (Al,Ga)As/GaAs heterointerface by applying a positive (negatie) gate bias. The 2D electron (hole) gas has a high electron (hole) mobility because of the reduction of the impurity scattering. This allows FET operation in the velocity saturation regime at low voltages for high transconductance transistors. The SAG approach is essential for HIGFET devices since electrical contact must be made directly to the 2D high mobility electron and hole gases, which are present only under the gates. The planar structure of this invention is important to achieve the high processing yield required for VLSI circuits. The insulating gate approach for both the n- and p-channel devices allows a larger voltage swing on the input gates without leakage or shorting. The insulating gates also improve the threshold voltage uniformity and control since the threshold voltage is much less critically dependent on the thickness and doping of the gate layer than normal MODFET device structures.